Add lor instruction

diff --git a/assembler.h b/assembler.h
index 0361831c59215de9aa372e0a5a898a50db1fff95..569aa9ef17c1c09e154d9545a00f82ee93b2614d 100644 (file)
--- a/assembler.h
+++ b/assembler.h
@@ -1,3 +1,3 @@
 #include "common.h"
 
-char opcodes_strings[N_INSTRUCTIONS][4] = {"nop", "inc", "dec", "lod", "ldl", "sav", "swp", "jmp", "jez", "hlt", "pts", "pfs", "dpx"};
+char opcodes_strings[N_INSTRUCTIONS][4] = {"nop", "inc", "dec", "lod", "ldl", "sav", "swp", "jmp", "jez", "hlt", "pts", "pfs", "dpx", "lor"};

diff --git a/common.h b/common.h
index a0a432df5923864f25725a5850a3471deeb36be7..6e8d295b3534bce3666e14daab7d1c5477bf5b95 100644 (file)
--- a/common.h
+++ b/common.h
@@ -1 +1 @@
-#define N_INSTRUCTIONS 13
+#define N_INSTRUCTIONS 14

diff --git a/opcodes.c b/opcodes.c
index 59078235993b02ab77a8879c403a8d1bf06c8770..42211a9c6b7afe88d13fdca04f839808394ae6ff 100644 (file)
--- a/opcodes.c
+++ b/opcodes.c
@@ -27,6 +27,8 @@
  * rex, 2 byte length - instruction + dest register - read from external(stdin) - blocks execution until 2 bytes are read
  *
  * dpx, 4 byte length - instruction + register with pixel location + register with R and G + register with B and A(R and B are first 8 bits, G and A are second 8 bits) 
+ *
+ * lor, 3 byte length - instruction + dest register + register containing address where to load from
  * 
  * all instructions are padded to 4 bytes
  */
@@ -178,4 +180,11 @@ void dpx(uint8_t pixel_num_reg, uint8_t red_green_reg, uint8_t blue_alpha_reg)
        return;
 }
 
-void (*opcodes[N_INSTRUCTIONS]) (uint8_t, uint8_t, uint8_t) = {nop, inc, dec, lod, ldl, sav, swp, jmp, jez, hlt, pts, pfs, dpx};
+void lor(uint8_t dest_reg, uint8_t unused_1, uint8_t mem_addr_reg)
+{
+       regs[dest_reg] = mem[regs[mem_addr_reg]];
+       current_instruction += 2;
+       return;
+}
+
+void (*opcodes[N_INSTRUCTIONS]) (uint8_t, uint8_t, uint8_t) = {nop, inc, dec, lod, ldl, sav, swp, jmp, jez, hlt, pts, pfs, dpx, lor};